In a field of designing a semiconductor integrated circuit such as a large scale integrated circuit (LSI), it is known to use a clock gating circuit to reduce consumption of electric power. The clock gating circuit controls supply of clock signals in accordance with enable signals. For example, the clock gating circuit stops the supply of the clock signals to a logic circuit such as a flip-flop when the logic circuit is not operating.
To design a semiconductor integrated circuit, a software tool, such as an electronic design automation (EDA) tool and a logic synthesizing tool, is widely used. In a typical situation, the tool loads existing circuit data representing a structure of a logic circuit including enable logics, and automatically inserts a clock gating circuit based on timing of the enable signals. As a result, the power consumption in the logic circuit may be reduced, but the clock gating circuit may be arranged downstream of a clock buffer, which adversely affects the performance of the logic circuit.